# Difference between revisions of "EECI 2013: Computer Session: TuLiP"

(2 intermediate revisions by the same user not shown) | |||

Line 1: | Line 1: | ||

− | {{eeci- | + | {{eeci-sp13 header|prev=RHTLP|next=Advanced Topics}} |

This lecture provides an overview of TuLiP, a Python-based software toolbox for the synthesis of embedded control software that is provably correct with respect to a GR[1] specifications. TuLiP combines routines for (1) finite state abstraction of control systems, (2) digital design synthesis from GR[1] specifications, and (3) receding horizon planning. The underlying digital design synthesis routine treats the environment as adversary; hence, the resulting controller is guaranteed to be correct for any admissible environment profile. TuLiP applies the receding horizon framework, allowing the synthesis problem to be broken into a set of smaller problems, and consequently alleviating the computational complexity of the synthesis procedure, while preserving the correctness guarantee. | This lecture provides an overview of TuLiP, a Python-based software toolbox for the synthesis of embedded control software that is provably correct with respect to a GR[1] specifications. TuLiP combines routines for (1) finite state abstraction of control systems, (2) digital design synthesis from GR[1] specifications, and (3) receding horizon planning. The underlying digital design synthesis routine treats the environment as adversary; hence, the resulting controller is guaranteed to be correct for any admissible environment profile. TuLiP applies the receding horizon framework, allowing the synthesis problem to be broken into a set of smaller problems, and consequently alleviating the computational complexity of the synthesis procedure, while preserving the correctness guarantee. | ||

Line 7: | Line 7: | ||

== Lecture Materials == | == Lecture Materials == | ||

− | * Lecture slides: [http://www.cds.caltech.edu/~ | + | * Lecture slides: [http://www.cds.caltech.edu/~murray/courses/eeci-sp13/C2_tulip-21Mar13.pdf TuLiP] |

* MATLAB plotting: [http://www.cds.caltech.edu/~murray/courses/eeci-sp12/plotRobotSim.m plotRobotSim.m], [http://www.cds.caltech.edu/~murray/courses/eeci-sp12/plotCarSim.m plotCarSim.m] | * MATLAB plotting: [http://www.cds.caltech.edu/~murray/courses/eeci-sp12/plotRobotSim.m plotRobotSim.m], [http://www.cds.caltech.edu/~murray/courses/eeci-sp12/plotCarSim.m plotCarSim.m] | ||

* [http://www.cds.caltech.edu/~murray/courses/eeci-sp12/tulip_examples.zip Example TuLiP files] (zip file): | * [http://www.cds.caltech.edu/~murray/courses/eeci-sp12/tulip_examples.zip Example TuLiP files] (zip file): |

## Latest revision as of 18:04, 2 March 2014

Prev: RHTLP | Course home | Next: Advanced Topics |

This lecture provides an overview of TuLiP, a Python-based software toolbox for the synthesis of embedded control software that is provably correct with respect to a GR[1] specifications. TuLiP combines routines for (1) finite state abstraction of control systems, (2) digital design synthesis from GR[1] specifications, and (3) receding horizon planning. The underlying digital design synthesis routine treats the environment as adversary; hence, the resulting controller is guaranteed to be correct for any admissible environment profile. TuLiP applies the receding horizon framework, allowing the synthesis problem to be broken into a set of smaller problems, and consequently alleviating the computational complexity of the synthesis procedure, while preserving the correctness guarantee.

A brief overview of TuLiP will be followed by hands-on exercises using the toolbox.

## Lecture Materials

- Lecture slides: TuLiP
- MATLAB plotting: plotRobotSim.m, plotCarSim.m
- Example TuLiP files (zip file):
- 6 cell robot, discrete state space: robot_discrete_simple.py
- 6 cell robot, with dynamics: robot_simple.py, robot_simple2.py (alternative formulation)

## Further Reading

TuLiP: A Software Toolbox for Receding Horizon Temporal Logic Planning, T. Wongpiromsarn, U. Topcu, N. Ozay, H. Xu and R. M. Murray, Hybrid Systems: Computation and Control, 2011.

## Additional Information

JTLV Project Home Site JTLV provides the framework for the underlying digital design synthesis routine used in TuLiP.