# EECI 2012: Computer Session: TuLiP

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This lecture provides an overview of TuLiP, a Python-based software toolbox for the synthesis of embedded control software that is provably correct with respect to a GR[1] specifications. TuLiP combines routines for (1) finite state abstraction of control systems, (2) digital design synthesis from GR[1] specifications, and (3) receding horizon planning. The underlying digital design synthesis routine treats the environment as adversary; hence, the resulting controller is guaranteed to be correct for any admissible environment profile. TuLiP applies the receding horizon framework, allowing the synthesis problem to be broken into a set of smaller problems, and consequently alleviating the computational complexity of the synthesis procedure, while preserving the correctness guarantee.

A brief overview of TuLiP will be followed by hands-on exercises using the toolbox.

## Lecture Materials

- Lecture slides: TuLiP (Exercises are at the end of the slides.)
- MATLAB plotting: [http://www.cds.caltech.edu/~murray/courses/afrl-sp12/plotNineCell.m
- Nine cell example: plotNineCell.m, nine_cell0.py, nine_cell_sim.txt
- Intersection example: plotIntersection.m, intersectionl0.py, intersection_sim.txt

## Further Reading

TuLiP: A Software Toolbox for Receding Horizon Temporal Logic Planning, T. Wongpiromsarn, U. Topcu, N. Ozay, H. Xu and R. M. Murray, Hybrid Systems: Computation and Control, 2011.

## Additional Information

JTLV Project Home Site JTLV provides the framework for the underlying digital design synthesis routine used in TuLiP.