Difference between revisions of "EECI 2012: Computer Session: TuLiP"
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== Additional Information == | == Additional Information == | ||
* <p>[http:// | * <p>[http://sourceforge.net/apps/mediawiki/tulip-control/index.php?title=Main_Page TuLiP on SourceForge] </p> | ||
* <p>[https://www.cds.caltech.edu/subversion/nok/rhtlp/trunk/doc/build/html/index.html TuLiP Documentation] For guest access, use ''anonymous'' as username with no password </p> | * <p>[https://www.cds.caltech.edu/subversion/nok/rhtlp/trunk/doc/build/html/index.html TuLiP Documentation] For guest access, use ''anonymous'' as username with no password </p> | ||
* <p>[http://jtlv.ysaar.net/ JTLV Project Home Site] JTLV provides the framework for the underlying digital design synthesis routine used in TuLiP. </p> | * <p>[http://jtlv.ysaar.net/ JTLV Project Home Site] JTLV provides the framework for the underlying digital design synthesis routine used in TuLiP. </p> | ||
Revision as of 03:39, 22 April 2012
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This lecture provides an overview of TuLiP, a Python-based software toolbox for the synthesis of embedded control software that is provably correct with respect to a GR[1] specifications. TuLiP combines routines for (1) finite state abstraction of control systems, (2) digital design synthesis from GR[1] specifications, and (3) receding horizon planning. The underlying digital design synthesis routine treats the environment as adversary; hence, the resulting controller is guaranteed to be correct for any admissible environment profile. TuLiP applies the receding horizon framework, allowing the synthesis problem to be broken into a set of smaller problems, and consequently alleviating the computational complexity of the synthesis procedure, while preserving the correctness guarantee.
A brief overview of TuLiP will be followed by hands-on exercises using the toolbox.
Lecture Materials
- Lecture slides: TuLiP
Further Reading
TuLiP: A Software Toolbox for Receding Horizon Temporal Logic Planning, T. Wongpiromsarn, U. Topcu, N. Ozay, H. Xu and R. M. Murray, Hybrid Systems: Computation and Control, 2011.
Additional Information
TuLiP Documentation For guest access, use anonymous as username with no password
JTLV Project Home Site JTLV provides the framework for the underlying digital design synthesis routine used in TuLiP.
